The present invention relates to an electrostatic discharge (ESD) protection scheme, and more particularly, to an electrostatic discharge protection circuit of which discharge elements have different characteristics, and a method thereof.
FIG. 1 is a diagram illustrating a prior art electrostatic discharge (ESD) protection circuit 10, which is utilized for protecting an integrated device 20 from being damaged by electrostatic discharging. The ESD protection circuit 10 comprises a low pass filter 11 consisting of a resistor R and a capacitor C; an inverter 12 consisting of a PMOS transistor Mpa and an NMOS transistor Mna; and a discharging circuit 13 consisting of an NMOS transistor Mnb. The connections between the low pass filter 11, the inverter 12, and the discharging circuit 13 are shown in FIG. 1. Furthermore, a first pad 14 is coupled to a terminal N1, a second pad 15 is coupled to a terminal N2, a third pad 16 is coupled to a terminal N5 for receiving an input signal to the integrated device 20, and two diodes D1, D2 are coupled to the terminal N5 for protecting the integrated device 20 from being damaged by the electrostatic discharging (ESD) signal that appears at the third pad 16.
Initially, the PMOS transistor Mpa, the NMOS transistor Mna, and the NMOS transistor Mnb are turned off. When the electrostatic discharging signal (the voltage Va) is induced to the first pad 14 or the third pad 16, the PMOS transistor Mpa will suddenly be turned on, and therefore the voltage at the terminal N4 will be charged instantaneously for turning on the NMOS transistor Mnb in order to discharge the voltage Va. Meanwhile, the low pass filter 11 proceeds to perform low pass filtering upon the voltage Va to generate the voltage Vc, so as to gradually increase the voltage Vc because of the low pass filtering characteristics of the resistor R and the capacitor C. After a time interval Δt′, the voltage Vc will turn on the NMOS transistor Mna to discharge the terminal N4. Then, the PMOS transistor Mpa and the NMOS transistor Mnb will be turned off. As can be seen from this description, the NMOS transistor Mna, the PMOS transistor Mpa, and the NMOS transistor Mnb typically are core devices, i.e. the low-voltage components, for increasing the sensitivity of the ESD protection circuit 10.
However, the low-voltage components, which can rapidly discharge the ESD signal, generally have large leakage currents. When the number of integrated devices increases, the number of ESD protection circuits needs to increase accordingly. Under the static condition, a very large leakage current will be generated due to all of the ESD protection circuits utilizing the low-voltage components.